Method for manufacturing a semiconductor device having a silicide region comprised of a silicide of a nickel alloy

ABSTRACT

To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2009-30179 filed onFeb. 12, 2009 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing method thereof, and more particularly, a semiconductordevice with a silicide region, and a manufacturing method thereof.

Some semiconductor devices include a silicide layer and a plug. Forexample, Japanese Unexamined Patent Publication No. 2008-205010 (PatentDocument 1) discloses a manufacturing method of such a semiconductordevice including the following steps.

A silicide layer which is a nickel silicide layer or a nickel-platinumsilicide layer is formed over a semiconductor substrate. Holes areformed in the silicide layer covered with an insulating film over thesemiconductor substrate by dry etching. A Ti layer is formed at an innersurface of each hole by a chemical vapor deposition (CVD) method. A Talayer is formed as a barrier metal layer on the Ti layer in the hole bysputtering. A copper layer is formed on the barrier layer to fill thehole, and the CMP is carried out thereby to form a copper plug.

As disclosed in the above patent document, a TiN layer may be formedbetween the barrier metal layer and the Ti layer by sputtering. Thebarrier metal layer is not limited to the Ta layer, and may be comprisedof any one of or a combination of a Ta layer, TiN, TaN, Ru, WN, W—N—C,Ti—Si—N_(x), Ta—Si—N_(x), and W—Si—N_(x).

RELATED ART DOCUMENTS Patent Documents

Patent Document 1

Japanese Unexamined Patent Publication No. 2008-205010

SUMMARY OF THE INVENTION

In the technique disclosed in the above patent document, an insulatingfilm is formed between the barrier metal layer (barrier metal film) andthe silicide layer (silicide region) in some cases. This results in anincrease in electrical resistance between the silicide region and theplug formed over the barrier metal film.

Accordingly, it is an object of the present invention to provide asemiconductor device that can reduce an electrical resistance between aplug and a silicide region, and a manufacturing method thereof.

A method for manufacturing a semiconductor device according to oneembodiment of the invention includes the following steps. At least onesemiconductor element, each having a silicide region comprised ofsilicide of a Ni (nickel) alloy, is formed over a semiconductorsubstrate. An interlayer insulating film is formed over the silicideregion. A through hole having an inner surface including a sidecomprised of the interlayer insulating film and a bottom surfacecomprised of the silicide region is formed in the interlayer insulatingfilm. A Ti(titanium) film covering the inner surface is formed by achemical vapor deposition process. At least a surface of the Ti film isnitrided so as to forma barrier metal film covering the inner surface. Aplug is formed to fill the through hole via the barrier metal film.

A semiconductor device according to another embodiment of the inventionincludes a semiconductor substrate, at least one semiconductor element,an interlayer insulating film, a barrier metal film, a plug, and anintermediate film. At least one semiconductor element is formed over thesemiconductor substrate. Each of the at least one semiconductor elementincludes a silicide region comprised of a silicide of an alloy of Ni andat least one element X selected from the group comprising Pt (platinum),V (vanadium), Pd (palladium), Zr (zirconium), Hf (hafnium), and Nb(niobium). The interlayer insulating film is provided over the at leastone semiconductor element. The interlayer insulating film is providedwith a through hole having an inner surface including a side comprisedof the interlayer insulating film and a bottom surface comprised of thesilicide region. The barrier metal film includes a TiN (titaniumnitride) film covering the inner surface. The plug fills the throughhole via the barrier metal film. The intermediate film is formed betweenthe silicide region and the barrier metal film. The total concentrationof Ti (titanium) —Si (silicon) —O (oxygen) —N (nitrogen) bond and Ti(titanium) —X (element X) —Si (silicon) —O (oxygen) —N (nitrogen) bondin the intermediate film is higher than that of Ti (titanium) —Ni(nickel) —O (oxygen) —N (nitrogen) bond.

The manufacturing method of the semiconductor device according to theembodiment of the invention activates the reaction between the Ti filmand the silicide region at the bottom surface of the through hole innitriding the Ti film, so that the part in the insulated state betweenthe Ti film and the silicide region is changed to an ohmic contactstate. The electrical resistance between the silicide region and thebarrier metal film formed by nitriding the Ti film is reduced. Thus, theelectrical resistance between the plug formed over the barrier metalfilm and the silicide region can be reduced.

In the semiconductor device according to the embodiment of theinvention, the concentration of Ti—Ni—O—N bond in the intermediate filmis small. Thus, the insulating oxide film, which may be generatedtogether with Ti—Ni—O—N bond, is prevented from being formed in theintermediate film. The electrical resistance of an electrical routebetween the barrier metal film and the silicide region via theintermediate film is reduced. Thus, the electrical resistance betweenthe plugs formed over the barrier metal film and the silicide regionscan be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view schematically showing the structure ofa semiconductor device according to a first embodiment of the invention,

FIG. 2 is a partial enlarged view of FIG. 1,

FIG. 3 is a flowchart for explaining a manufacturing method of thesemiconductor device in the first embodiment of the invention,

FIG. 4 is a flowchart for explaining processes for forming a silicideregion shown in FIG. 3,

FIG. 5 is a flowchart for explaining processes for forming through holesshown in FIG. 3,

FIG. 6 is a flowchart for explaining processes for forming a barriermetal film shown in FIG. 3,

FIG. 7 is a cross-sectional view schematically showing a first step ofthe manufacturing method of the semiconductor device in the firstembodiment of the invention,

FIG. 8 is a cross-sectional view schematically showing a second step ofthe manufacturing method of the semiconductor device in the firstembodiment of the invention,

FIG. 9 is a cross-sectional view schematically showing a third step ofthe manufacturing method of the semiconductor device in the firstembodiment of the invention,

FIG. 10 is a cross-sectional view schematically showing a fourth step ofthe manufacturing method of the semiconductor device in the firstembodiment of the invention,

FIG. 11 is a cross-sectional view schematically showing a fifth step ofthe manufacturing method of the semiconductor device in the firstembodiment of the invention,

FIG. 12 is a graph showing an example of the measurement result of anelectrical resistance between a plug and a silicide region in each of anexample of the first embodiment of the invention, and first and secondcomparative examples,

FIG. 13 is a graph showing an example of the analysis results of adry-etched surface of a silicide region by X-ray photoelectronspectroscopy in each of the example of the first embodiment of theinvention and a third comparative example,

FIG. 14 is a graph showing an example of the analysis results of a C 1sspectrum of a surface obtained after formation of a Ti film by use ofthe X-ray photoelectron spectroscopy in a fourth comparative example,

FIG. 15 is a graph showing an example of the analysis results of a N 1sspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fourth comparativeexample,

FIG. 16 is a graph showing an example of the analysis results of a N 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fourth comparativeexample,

FIG. 17 is a graph showing an example of the analysis results of an O 1sspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fourth comparativeexample,

FIG. 18 is a graph showing an example of the analysis results of a Si 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fourth comparativeexample,

FIG. 19 is a graph showing an example of the analysis results of a Ti 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fourth comparativeexample,

FIG. 20 is a graph showing an example of the analysis results of a C 1sspectrum of a surface obtained after formation of a Ti film by use ofthe X-ray photoelectron spectroscopy in a fifth comparative example,

FIG. 21 is a graph showing an example of the analysis results of a N 1sspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fifth comparativeexample,

FIG. 22 is a graph showing an example of the analysis results of a Ni 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fifth comparativeexample,

FIG. 23 is a graph showing an example of the analysis results of an O 1sspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fifth comparativeexample,

FIG. 24 is a graph showing an example of the analysis results of a Si 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fifth comparativeexample, and

FIG. 25 is a graph showing an example of the analysis results of a Ti 2pspectrum of the surface obtained after formation of the Ti film by useof the X-ray photoelectron spectroscopy in the fifth comparativeexample, and

FIG. 26 is a cross-sectional view schematically showing the structure ofa semiconductor device according to a second embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention will be described below based onthe accompanying drawings.

FIRST PREFERRED EMBODIMENT

First, the structure of a semiconductor device according to thisembodiment will be described below.

Referring to FIGS. 1 and 2, the semiconductor device of this embodimentmainly includes a semiconductor substrate SB, a complementary metaloxide semiconductor (CMOS), an interlayer insulating film ILD1, abarrier metal film BM, a plug PG, an intermediate film IM, an elementisolation insulating film ISL, a metal wiring layer ML, and aninterlayer insulating film ILD2. The CMOS includes n-type and p-typetransistors separated from each other by the element isolationinsulating film ISL, namely, an n-MOS transistor NT (semiconductorelement) and a p-MOS transistor PT (semiconductor element).

The n-MOS transistor NT is formed over the semiconductor substrate SB.The n-MOS transistor NT includes silicide regions SCs and SCg, a gateelectrode including a polysilicon portion PS, source and drain regionsSD1 and SD1, extension regions ET1 and ET1, a p-well WL1, a gateinsulating film GI, and sidewalls SWs.

Each of the silicide regions SCs and SCg is formed of a Ni alloysilicide. More specifically, each of the silicide regions SCs and SCg isformed of a silicide of an alloy of Ni and at least one element Xselected from the group comprising Pt, V, Pd, Zr, Hf, and Nb. Thesilicide regions SCs and SCg include a first silicide portion SCs incontact with the source drain region SD1 and a second silicide portionSCg serving as at least a part of the gate electrode.

The p-MOS transistor PT is formed over the semiconductor substrate SB.The p-MOS transistor PT includes silicide regions SCs and SCg, a gateelectrode including a polysilicon portion PS, source and drain regionsSD2 and SD2, extension regions ET2 and ET2, an n-well WL2, a gateinsulating film GI, and sidewalls SWs.

Each of the silicide regions SCs and SCg is formed of a Ni alloysilicide. More specifically, each of the silicide regions SCs and SCg isformed of an alloy of Ni and at least one element X selected from thegroup comprising Pt, V, Pd, Zr, Hf, and Nb. The silicide regions SCs andSCg include a first silicide portion SCs in contact with thesource/drain region SD2 and a second silicide portion SCg serving as atleast a part of the gate electrode.

An interlayer insulating film ILD1 is provided over the p-MOS transistorPT and the n-MOS transistor NT. The interlayer insulating film ILD1 isprovided with through holes THs, each having an inner surface includinga side comprised of the interlayer insulating film ILD1 and a bottomsurface comprised of the intermediate film IM.

The barrier metal film BM covers the inner surface of each through holeTH. The barrier metal film BM is comprised of a Ti film having at leastone surface (on the plug PG side) thereof nitrided. That is, the barriermetal film BM includes a TiN film covering the inner surface of thethrough hole TH.

The plug PG fills the through hole TH via the barrier metal film BM. Theplug PG is formed of, for example, W (tungsten).

The intermediate film IM is formed between each of the silicide regionsSCs and SCg and the barrier metal film BM. The intermediate film IMincludes a compound having a Ti—Si—O—N bond and a Ti—X—Si—O—N bond. Thetotal concentration of the Ti—Si—O—N bond and the Ti—X—Si—O—N bond inthe intermediate film IM is higher than that of the Ti—Ni—O—N bond.

Now, the outline of a manufacturing method of the semiconductor devicein this embodiment will be described below. Referring to FIGS. 1 and 3,the semiconductor substrate SB is prepared in step S1. Then, the elementisolation insulating film ISL, the p-well WL1, the n-well WL2, the gateinsulating film GI, the source and drain regions SD1 and SD2, theextension regions ET1 and ET2, the polysilicon portion PS, and thesidewalls SWs are formed.

Referring to FIGS. 3 and 7, in step S2, the first silicide portion SCsand the second silicide portion SCg are formed as a silicide region. Thesecond silicide portion SCg together with the polysilicon portion PSforms the gate electrode. Specifically, the following processes instepsS21 to S24 (FIG. 4) are performed.

In step S21, a high-melting-point metal film (not shown) is formed tocover the polysilicon portion PS and the source and drain regions SD1and SD2 in a vacuum unit evacuated to vacuum. The high-melting-pointmetal film is comprised of an alloy (Ni alloy) containing Ni as aprincipal component. More specifically, the high-melting-point metalfilm is comprised of material to which at least one element X selectedfrom the group comprising Pt, V, Pd, Zr, Hf, and Nb is added. The amountof addition is less than 10 atom %. The formation method of thehigh-melting-point metal film is, for example, a physical vapordeposition (PVD) method or a CVD method.

In step S22, an oxidation preventing film (not shown) made ofhigh-melting-point metal is formed over the high-melting-point metalfilm in the vacuum unit kept in a vacuum so as to prevent the oxidationof the above-mentioned high-melting-point metal film. The oxidationpreventing film is, for example, a TiN film formed by the CVD method orPVD method.

In step S23, a silicide process is performed. In other words, heattreatment is performed to react the above high-melting-point metal filmwith the polysilicon portion PS and each of the source and drain regionsSD1 and SD2. Specifically, for example, rapid thermal anneal (RTA) isperformed thereby to form the first silicide portion SCs in contact withthe source/drain region and the second silicide region SCg serving as atleast a part of the gate electrode.

In step S24, the above-mentioned oxidation preventing film is removed.After the above steps S21 to S24 (step S2), the n-MOS transistor NT andthe p-MOS transistor PT, each having the silicide regions SCs and SCg,are formed.

Referring to FIGS. 3 and 8, in step S3, the interlayer insulating filmILD1 is formed over the silicide regions SCs and SCg.

In step S4, through-holes THs are formed in the interlayer insulatingfilm ILD1 with reference to FIGS. 3 and 8. Specifically, the followingprocesses in steps S41 to S45 (see FIG. 5) will be described.

In step S41, a resist mask (not shown) having a pattern corresponding toa pattern of the through holes THs is formed over the interlayerinsulating film ILD1. Specifically, application, exposure anddevelopment of the photoresist are performed.

In step S42, dry etching is performed using the above resist mask toform the through holes THs.

In step S43, ashing is performed to remove the above resist mask. Instep S44, chemical cleaning is performed so as to remove the residue oneach through hole TH after the step S43. The chemical cleaning isperformed at a temperature of 100° C. or less using, for example, amixed gas of NH₃ and HF.

Instep S45, annealing is performed to remove by-products generated inthe above chemical cleaning. Specifically, the annealing is performed ata temperature not less than 100° C. nor more than 300° C. in the samechamber as that in which the chemical cleaning is performed, or inanother in-situ chamber.

In the processes of steps S41 to S45 described above (in step S4), thethrough hole TH having the inner surface, including the side comprisedof the interlayer insulating film ILD1 and the bottom surface comprisedof the silicide region SCs or SCg, is formed in the interlayerinsulating film ILD1.

Mainly referring to FIG. 3, in step S5, the barrier metal film BM (seeFIG. 10) is formed to cover the inner surface of the through hole.Specifically, the following processes in step S51 and S52 (see FIG. 6)will be performed.

After formation of the through holes TH (in step S4) , in step S51, a Tifilm TF (see FIG. 9) covering the inner surface of each through hole THis formed under in-situ by the CVD method. The coating temperature inthe CVD method is, for example, 550° C. or less.

In formation of the Ti film TF, an interfacial reaction is causedbetween each of the silicide regions SCs and SCg and the Ti film TF toform a film IMi between each of the silicide regions SCs and SCg and theTi film TF. The film IMi may have a part including an insulator. In thiscase, the part in an insulated state is formed between each of thesilicide regions SCs and SCg and the Ti film TF. Further, as shown inFIG. 9, the film IMi is formed within each of the silicide regions SCsand SCg.

In step S52, at least a surface of the Ti film TF (see FIG. 9) isnitrided thereby to form the barrier metal film BM (see FIG. 10). In thenitriding process, the Ti film TF is nitrided, and the intrusion of N(nitrogen) atoms into the film IMi is also caused. Further, the reactionbetween each of the silicide regions SCs and SCg and the Ti film TF isalso activated in the nitriding process. Thus, the intermediate film IM(see FIG. 10) is formed from the film IMi (see FIG. 9). The intermediatefilm IM has at least either a Ti (titanium) —Si (silicon) —O (oxygen) —N(nitrogen) bond or a Ti (titanium) —X (element X) —Si (silicon) —O(oxygen) —N (nitrogen) bond, whose concentration in total is higher thanthat of Ti (titanium) —Ni (nickel) —O (oxygen) —N (nitrogen) bond. Information of the intermediate film IM, the above-mentioned part in theinsulated state between each of the silicide regions SCs and SCg and thebarrier metal film BM is easily changed to an ohmic contact state.

Preferably, the Ti film TF is nitrided at a temperature of 400° C. ormore so as to sufficiently perform the nitriding process, and at atemperature of 550° C. or less so as to prevent agglomeration of thesilicide regions SCs and SCg. The nitriding of the Ti film TF ispreferably performed by exposing the Ti film TF to an atmospherecontaining plasma. The plasma is more preferably NH₃ plasma generatedusing NH₃ gas.

In the above steps S51 and S52 (step S5), the barrier metal BM isformed.

Referring to FIGS. 3 and 11, in step S6, the plugs PG are formed to fillthe through holes THs. Specifically, first, a W film is formed by theCVD method to fill each through hole TH. Then, the W film and thebarrier metal film BM are removed by being ground by the CMP method soas to expose the upper surface of the interlayer insulating film ILD1.

Referring to FIGS. 3 and 1, in step S7, metal wiring layers ML and MLare formed so as to be respectively coupled to the first silicideportion SCs and the second silicide portion SCg by the plugs PGs.Further, the interlayer insulating film ILD2 is also formed between themetal wiring layers ML and ML. The metal wiring layer ML is comprisedof, for example, an Al (aluminum) wiring or a Cu (copper) wiring.

As mentioned above, the semiconductor device of this embodiment (seeFIG. 1) is obtained. According to this embodiment, the reaction betweenthe Ti film TF and each of the silicide regions SCs and SCg is activatedat the bottom of each through hole TH in nitriding (see FIG. 6: in stepS51) of the Ti film TF (see FIG. 9), so that the insulated part betweenthe Ti film TF and each of the silicide regions SCs and SCg is changedto the ohmic contact state. An electrical resistance between each of thesilicide regions SCs and SCg and the barrier metal film BM (see FIG. 10)is reduced. Thus, an electrical resistance between the plug PG formedover the barrier metal film BM and each of the silicide regions SCs andSCg can be reduced.

Exposure of the Ti film TF to the atmosphere containing plasma canfurther activate the above reaction. The use of NH₃ plasma as the plasmacan activate especially the above-described reaction. The NH₃ plasma canremove Cl (chlorine) contained in the Ti film TF therefrom.

The highly stable Ni—X bond is formed in the silicide regions SCs andSCg by allowing the silicide to contain the element X. Even when thesilicide regions SCs and SCg exposed to the bottom of each through holeTH is oxidized due to influences of gas for dry etching (see FIG. 5: instep S42) or the like, the Ni—X bond can be maintained at the surface ofeach of the silicide regions SCs and SCg. That is, the above oxidationcan prevent the bond at the surface of the silicide regions SCs and SCgfrom changing to the Ni—O bond.

If the rate of the Ni—O bond at the surface of each of the silicideregions SCs and SCg becomes large, an oxide film tends to be easilyformed between each of the silicide regions SCs and SCg and the Ti filmTF when the Ti film TF is formed over the silicide regions SCs and SCg(see FIG. 6: in step S51). The influence of the oxide film makes itdifficult to make ohmic electrical contact between each of the silicideregions SCs and SCg and the barrier metal film BM including the Ti filmTF. In some cases, the electrical contact cannot be obtained. In thiscase, even if an initial resistance between each of the silicide regionsSCs and SCg and the barrier film BM is sufficiently low, the oxide filmmay react with the barrier metal film during storage of thesemiconductor device at high temperature to cause fluctuations inresistance, which possibly reduces the reliability of the semiconductordevice.

When the semiconductor device includes both the n-MOS transistor NT andthe p-MOS transistor PT, the thickness of the above oxide film of then-MOS transistor NT tends to become larger than that of the p-MOStransistor PT. Thus, when some means is taken to surely remove the oxidefilm from the n-MOS transistor NT, the silicide regions SCs and SCg maybe removed from the p-MOS transistor PT. As a result, the yield of thesemiconductor devices may be reduced. However, this embodimenteliminates the necessity of removal of such an oxide film, and thus canenhance the yield of the semiconductor devices.

Since the concentration of Ti—Ni—O—N bond in the intermediate film IM islow, the formation of the above oxide film, which may be easilygenerated together with the Ti—Ni—O—N bond in the intermediate film IM,is suppressed. An electrical route is formed between each of thesilicide regions SCs and SCg and the barrier metal film BM via theintermediate film IM, and the electrical resistance of the electricalroute is reduced. Thus, the electrical resistance between the silicideregions SCs and SCg and the plug PG formed over the barrier metal filmBM can be made small.

As described above, this embodiment can suppress the electricalresistance between each of the silicide regions SCs and SCg and the plugPG. The following will describe examples of this embodiment by comparingthe examination results of this embodiment to those of comparativeexamples.

The formation of a barrier metal film in a first comparative examplediffers from this embodiment in that the barrier metal film formationinvolves formation of a Ti film by a PVD method, and formation of a TiNfilm over the Ti film by the CVD method. The formation of a barriermetal film in a second comparative example is performed in the same wayas that of the first comparative example, so that a silicide region ofthe second comparative example is formed of a simple Ni silicide, andnot a Ni alloy. In each of this embodiment and the first and secondcomparative examples, the electrical resistance R (Ω) between thesilicide region and the plug is measured.

FIG. 12 shows cumulative probabilities CP (%) of the above electricalresistances R in this embodiment, the first comparative example, and thesecond comparative example as plots Pa, Pb, and Pc. As compared to thisembodiment (plot Pa), the first comparative example (plot Pb) has theelectrical resistance R increased, and the second comparative example(plot Pc) leads to variations in electrical resistance R. This resulthas shown that this embodiment can stably suppress the electricalresistance between each of the silicide regions SCs and SCg and the plugPG.

A silicide region in the third comparative example differs from that ofthis embodiment in that the silicide region is formed of the simple Nisilicide (NiSi_(x)) and not a Ni alloy. In contrast, the silicide regionof this embodiment is comprised of NiPtSi_(x). The dry-etched surface ofthe silicide region is analyzed by X-ray photoelectron spectroscopy.

With reference to FIG. 13, the analysis results provided by the aboveX-ray photoelectron spectroscopy are shown while the horizontal axis isa binding energy BE (eV), and the longitudinal axis is a count CNT (/s).This result has shown that the surface oxidation of the silicide regionof this embodiment is suppressed as compared to the third comparativeexample.

The fourth and fifth comparative examples will be describe below. Thesilicide region in each of the fourth and fifth comparative examples iscomprised of NiSi_(x). In the fourth comparative example, a Ti film isformed over the silicide region by the PVD method. In the fifthcomparative example, a Ti film is formed over the silicide region by theCVD method.

Referring to FIGS. 14 to 19 and FIGS. 20 to 25, in the fourth and fifthcomparative examples, the surface obtained after formation of the Tifilm is analyzed by the X-ray photoelectron spectroscopy. This analysisresult has shown that the influences given by the formation methods ofthe Ti film are remarkable at each of Ni2p and Si2p. That is, a Ni peakat the Ni2p bond is apparently detected in the case of the PVD method(of the fourth comparative example), and a bonding peak correspondingthereto is not detected in the case of the CVD method (of the fifthcomparative example). No Si peak at the Si2p bond is apparently detectedin the case of the PVD method, and a Si peak is apparently detected inthe case of the CVD method. As explained in the description of the firstembodiment, the intermediate film IM contains at least either a Ti(titanium) —Si (silicon) —O (oxygen) —N (nitrogen) bond or a Ti(titanium) —X (element X) —Si (silicon) —O (oxygen) —N (nitrogen) bond.The total concentration of the above-mentioned bond in the intermediatefilm is higher than the Ti (titanium) —Ni (nickel) —O (oxygen) —N(nitrogen) bond. In the fourth comparative example, the Ni peak isdetected on the surface obtained after formation of the Ti film. Thismeans that the amount of Ni serving as non-ohmic contact material, suchas Ti (titanium) —Ni (nickel) —O (oxygen) —N (nitrogen) bond, is great,and that the formation of the Ti film by the PVD method is not goodbecause it makes the ohmic characteristics worse. In the fifthcomparative example, the Si peak is detected on the surface obtainedafter formation of the Ti film. This means that the amount of Si servingas good ohmic contact material, such as Ti (titanium) —Si (silicon) —0(oxygen) —N (nitrogen) bond, or Ti (titanium) —X (element X) —Si(silicon) —O (oxygen) —N (nitrogen) bond, is great, and that theformation of the Ti film by the CVD method makes the ohmiccharacteristics better.

SECOND PREFERRED EMBODIMENT

Referring to FIG. 26, a semiconductor device of this embodiment isprovided with silicide regions SCs1 and SCg1 in a region above a p-wellWL1 (in a region where an n-MOS transistor NT is formed), and silicideregions SCs2 and SCg2 in a region above an n-well WL2 (in a region wherea p-MOS transistor PT is formed), instead of the silicide regions SCsand SCg of the first embodiment. The silicide regions SCs1 and SCg1 eachinclude a silicide of an alloy of Ni and at least one element X1selected from the group comprising Pt, V, and Pd. The silicide regionsSCs2 or SCg2 each include a silicide of an alloy of Ni and at least oneelement X2 selected from the group comprising Zr, Hf, and Nb.

In the semiconductor device of this embodiment, instead of theintermediate film IM of the first embodiment, an intermediate film IM1is provided in a region above the p-well WL1 (in a region where then-MOS transistor NT is formed) , and an intermediate film IM2 isprovided in a region above the n-well WL2 (in a region where the p-MOStransistor PT is formed). The intermediate film IM1 is formed of acompound having Ti—Si—O—N bond and Ti—X1—Si—O—N bond. The totalconcentration of Ti—Si—O—N bond and Ti—Xi—Si—O—N bond in theintermediate film IM1 is higher than that of Ti—Ni—O—N bond therein. Theintermediate film IM2 is formed of a compound having Ti—Si—O—N bond andTi—X2—Si—O—N bond. The total concentration of Ti—Si—O—N bond andTi—X2—Si—O—N bond in the intermediate film IM2 is higher than that ofTi—Ni—O—N bond therein.

Now, a manufacturing method of the semiconductor device according tothis embodiment will be described below. In this embodiment, the processin step S2 (see FIG. 3) is individually performed on each of the regionsabove the p-well WL1 and the n-well WL2.

The following processes are performed on the region above the p-wellWL1. An oxide film which is a silicide block layer is formed over thesemiconductor substrate SB, for example, by the CVD method. Then, theoxide film on the p-well WL1 is selectively removed by anisotropicetching using the photolithography technique and etching technique.Thereafter, a high-melting-point metal film (not shown) is formed overthe p-well WL1 region in the vacuum unit evacuated to vacuum so as tocover the polysilicon portion PS and the source and drain regions SD1s.The high-melting-point metal film is formed of an alloy (Ni alloy)containing Ni as a principal component, more specifically, material towhich element X1 is added. The amount of addition of the element X1 issmaller than 10 atom %. The formation method of the high-melting pointmetal film is, for example, the PVD method or CVD method. Next, the sameprocesses as those in steps S22 to S24 (see FIG. 4) of the firstembodiment are performed. Thereafter, the above oxide film is removed bythe so-called RCA cleaning.

The following processes are performed on the region above the n-wellWL2. An oxide film which is a silicide block layer is formed over thesemiconductor substrate SB, for example, by the CVD method. Then, theoxide film on the n-well WL2 is selectively removed by anisotropicetching using the photolithography technique and etching technique.Thereafter, a high-melting-point metal film (not shown) is formed overthe n-well WL2 region in the vacuum unit evacuated to vacuum so as tocover the polysilicon portion PS and the source and drain regions SD2.The high-melting-point metal film is formed of an alloy (Ni alloy)containing Ni as a principal component, more specifically, material towhich element X2 is added. The amount of addition of the element X2 issmaller than 10 atom %. The formation method of the high-melting- pointmetal film is, for example, the PVD method or CVD method. Next, the sameprocesses as those in steps S22 to S24 (see FIG. 4) of the firstembodiment are performed. Thereafter, the above oxide film is removed bythe so-called RCA cleaning.

The order of the processes performed on the regions above the respectivep-well WL1 and n-well WL2 described above can be replaced.

The structures of other components except for the above-mentionedelements are substantially the same as those of the first embodiment asdescribed above. The same or like components are designated by the samereference characters, and a description thereof will not be repeated.

According to this embodiment, the same effect as that of the firstembodiment is obtained. The n-MOS transistor NT and the p-MOS transistorPT can include different silicide materials in use.

Although the nitriding process of the Ti film TF is performed using theplasma (see FIG. 6, in step S52) in the above description, the nitridingmethod is not limited thereto. For example, the Ti film TF heated may beexposed to an atmosphere containing nitrogen gas without using theplasma.

The chemical cleaning (see FIG. 5, in step S44) may be performed in theplasma so as to improve a removing capability of the residue.

It is to be understood that the foregoing description of the preferredembodiments of the invention has been presented for the purposes ofillustration and example only from all viewpoints, and does not limitthe invention to the precise form disclosed. It is intended that thescope of the invention be limited not by the above detailed description,but rather by the claims appended thereto. All modifications areintended to fall within the spirit and scope of the appended claims andtheir equivalents.

The invention can be advantageously applied to, in particular,semiconductor devices with a silicide region, and a manufacturing methodthereof.

1-7. (canceled)
 8. A semiconductor device, comprising: a semiconductorsubstrate; at least one semiconductor element formed over thesemiconductor substrate, each of said at least one semiconductor elementincluding a silicide region comprised of a silicide of an alloy of Niand at least one element X selected from the group comprising Pt, V, Pd,Zr, Hf and Nb; an interlayer insulating film provided over said at leastone semiconductor element, said interlayer insulating film beingprovided with a through hole having an inner surface including a sidecomprised of the interlayer insulating film and a bottom surfacecomprised of the silicide region; a barrier metal film including a TiNfilm covering the inner surface; a plug filling the through hole via thebarrier metal film; and an intermediate film formed between the silicideregion and the barrier metal film, wherein a total concentration ofTi—Si—O—N bond and Ti—X—Si—O—N bond in the intermediate film is higherthan that of Ti—Ni—O—N bond.
 9. The semiconductor device according toclaim 8, wherein said at least one semiconductor element includes atleast one transistor, each having a source/drain region and a gateelectrode, and wherein the silicide region includes a first silicideportion in contact with the source/drain region, and a second silicideportion serving as at least a part of the gate electrode.
 10. Thesemiconductor device according to claim 8, wherein said at least onetransistor includes an n-type transistor and a p-type transistor.